• overview
  • overview
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R&D Division of 
Electronic Components

   
  Organization that brings the future through
Science & Technology

Fan Out - WLP(Wafer Level) & PLP(Panel Level) Solution

 

Small form-factor package which eliminates wire-bonding, flip chip bump and substrate. With an excellent electrical performance this is a suitable package for RF device, PMIC, and low power consumption MCU.

 

Technology

Implementation of Fan-out Package by Core Technology of Chip Assembly / EMC Encapsulation / RDL & Passivation Build-up based on Wafer Level & Panel Level



FO-WLP (Wafer Level Package)
300mm round







nPLP (Panel Level Package)
600x600mm panel


Features
ㆍFreedom of Routing & Design
ㆍExtremely Thin & Small form factor
ㆍFine L/S and Increased I/O density, Shorten interconnection
ㆍExcellent electrical & Thermal performance & High reliability
ㆍAssembly of Known good die and Cost competitiveness
Application
ㆍConsumer : Mobile / Smartphone / IoT
 - RF, Power, Audio, etc. / Antenna Switch / Fingerprint & Bio Sensor
ㆍ Automotive : ADAS / Radar Sensor
 - Receiver, Transceiver & Voltage Control Oscillator